Working principle of FIR filter

　　Before entering the FIR filter, the analog signal shall be converted to digital signal through A/D device; In order to avoid signal processing distortion, the sampling speed of the signal must meet the Shannon sampling theorem. Generally, 4-5 times of the upper limit of the signal frequency is taken as the sampling frequency; Generally, a progressive forced A/D converter with high speed can be used. Whether the FIR filter is designed by multiplying and accumulating method or distributed algorithm, the output data of the filter is a series of sequences. To make it intuitively reflected, digital to analog conversion is also required. Therefore, the output of the FIR filter composed of FPGA must be connected to an external D/A module. FPGA has a regular internal logic array and rich wiring resources, which is particularly suitable for digital signal processing tasks. Compared with the general DSP chip dominated by serial operation, it has better parallelism and scalability. Using the fast algorithm of FPGA multiplication and accumulation, you can design a high-speed FIR digital filter.

Read recommendations:

Application of Varistor in Solid State Relay Circuit Overvoltage Protection Circuit.Mini PIR Sensor

U-type plug-in NTC thermistor temperature sensor.Infrared sensing module wholesale

PND103F3950FTU102

8308-A PIR lens

P914 Digital sensor